1. Field of the Invention
The present invention relates to a phase interpolating apparatus and associated phase interpolating method, and more particularly, to a phase interpolating apparatus and method capable of predicting interpolation and switching phase to be interpolated in advanced.
2. Description of the Prior Art
A phase interpolating apparatus is widely used in modern electronics because it is used to generate multiple clock signals having different phases based on few clock signals. Please refer to FIG. 1, which illustrates a block diagram of a phase interpolating apparatus 100 in the prior art. As shown in FIG. 1, the phase interpolating apparatus 100 in the prior art comprises a phase interpolator 101 and multiplexers (denoted as Mux in abbreviation) 103 and 105. The multiplexer 103 is used to receive input clock signals CLK0, CLK2, CLK4, and CLK6 having different even phases P0, P2, P4, and P6, respectively, and is also used to select one of the inputs to the phase interpolator 101. Similarly, the multiplexer 105 is used to receive input clock signals CLK1, CLK3, CLK5, and CLK7 having different odd phases P1, P3, P5, and P7, respectively, and is also used to select one of the inputs to the phase interpolator 101. The phase interpolator 101 is used to generate an interpolated clock signal CIS according to the received clock signals.
However, when a traditional phase interpolating apparatus switches clock signals to be interpolated, an unexpected voltage pulse is sometimes generated. Please refer to FIG. 2, which depicts a diagram for explaining how voltage pulse is generated in the prior art. In the example shown in FIG. 2, the phase interpolating apparatus 100 generates the interpolated clock signal CIS based on the clock signal CLK0 having phase P0 at the upper side and the clock signal CLK1 having phase P1 at the lower side at first. Then the phase interpolating apparatus 100 switches to the clock signal CLK2 from the clock signal CLK0 to generate the interpolated clock signal CIS with the clock signal CLK1. As shown in FIG. 2(a), the interpolated clock signal CIS at timing points T1, T2, T3, and T4 are interpolated according to the clock signals CLK0 and CLK1 at the same timing points T1, T2, T3, and T4.
As shown in FIG. 2(b), at the moment that the clock signal at the upper side to be interpolated is switched from the clock signal CLK0 having phase P0 to the clock signal CLK2 having phase P2, a temporary transition state is generated because of the switch transition. In this temporary transition state, value of the clock signal CLK0 would be residuary and cause the interpolated clock signal CIS to display error. For example, at the timing point T2 shown in FIG. 2(b), the voltage level of the clock signal CLK2 is low and so is the clock signal CLK1, the voltage level of the interpolated clock signal CIS should be low accordingly. But the clock signal CLK0 is residuary (represented by dashed line). Moreover, the voltage level of the clock signal CLK0 at timing point T2 is high. Therefore a voltage pulse P would be interpolated as the interpolated clock signal CIS at timing point T2. Even though value of the interpolated clock signal CIS is correct after timing point T2, the voltage pulse P effects accuracy overall. Please refer to FIG. 2(c), the upper input signal is switched to the clock signal CLK2 after timing point T2, correct values of interpolated clock signal can be read at timing points T3 and T4. However, the voltage pulse P which appeared at the timing point T2 cause un-recoverable errors. Such errors make the interpolated clock signal display un-normal surge or decays, so the waveform becomes incorrect.
In order to solve the above problem, several solutions were already provided in the prior art. One of these solutions is to wait a predetermined time interval after the switch, and then generate the interpolated clock signal. However, the processing speed is slower in this configuration, and more complicated logic circuits are needed to control the switch and the interpolation separately.